High-Speed Data Transfer

Eiger Peak is a team of electrical engineering undergraduate seniors working to create a phase-lock loop for their senior project. The team is composed of seven members – Nicholas Bybee, Stuart Anderson, Jacob Atkinson, Reuben Morrell, Anthony Bailey, Mitch Crane and Anton Arriaga, all working under the supervision of professor Armin Tajalli.

The team is learning the process of creating current mode logic amplifiers, which are used for transmitting data at very high speeds. A current mode logic amplifier is the basic building block for the phase-lock loop, which is used to control frequencies of transmitted waves. It is like racecars going around a racetrack, where signals are used to convey to the cars when they can pass each other and when to maintain a uniform speed and distance.

Their investigation into phase-lock loops requires specific design parameters such as power consumption, target specifications, fabrication technology and circuit topology. With these in mind, the team is working to create a methodology to design optimal current mode logic amplifiers.

Efficiency is the current focus for the team, as they try to decrease the power demand of any chips they use in designing the phase-lock loop. Too large of a power demand will overheat the circuits and destroy important components, but too little power and data is sent too slowly. Increasing throughput is one possibility, which means finding ways to send more data at once.

The team hopes their research into phase-lock loops will find both national and international acclaim. From all the work the team put into their project, they hope the paper will make a mark on electrical engineering advances. “It has pushed a lot of our buttons,” Anderson said. “It has challenged our learning curve, challenged our motivations. It is not textbook learning anymore; we are the ones making discoveries and understanding where this technology goes.”

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